Integrated circuit-based quantum chips, composed of superconducting or semiconductor-based qubits, are delicate and susceptible to various sources of errors. These errors arise from factors such as thermal noise, electromagnetic interference, and imperfections in their fabrication process.

Without effective metrology, inspection and testing methodologies, these errors will therefore propagate and compromise the accuracy of quantum computations. Only a fast feedback loop between scalable design, fabrication and testing will enable the large-scale fabrication and control of quantum chips. This development cycle is essential to pave the way to commercial quantum advantage.

In contrast to conventional CMOS metrology and testing, no simple correlations exist between conventional optical inspection and information processing parameters of a quantum chip. The full performance of a quantum chip can therefore only be measured by calibrating and tuning up the qubits to levels of quantum computing operating conditions. Tuning up qubits requires a framework for executing physics-based control sequences and protocols that also allow for the automation of the tasks usually performed manually by experienced quantum engineers.

Superconducting as well as semiconductor-based quantum chips do not operate in ambient conditions, but need to be isolated and shielded, involving high vacuum, ultra-low temperatures, and low-power microwave electromagnetic signals. That also requires different methods of diagnostics, testing and qualification as compared to standard CMOS metrology.

Equipment for quantum chip testing therefore needs to consist of a control framework, room temperature control electronics, cryogenic input and output lines ensuring DC and low-loss microwave signal propagation and a shielded cryogenic environment at milli-Kelvin temperatures.