Talk on quantum chip testing at SPIE Advanced Lithography + Patterning 2024

Thorsten Last presented at the SPIE Advanced Lithography and Patterning conference in San José, US. He explained some of the intricacies of quantum chip testing, as well as the large gap between required and available testing throughput.

SPIE Advanced Lithography Patterning 2024 Thorsten Last quantum chip test equipment semicon industry

Thorsten Last presents at SPIE Advanced Lithography and Patterning 2024

The SPIE Advanced Lithography and Patterning conference is one of the events where the semiconductor industry congregates to share announcements and insights.

The talk by Thorsten Last, co-founder and director at OrangeQS, on ‘Test and measurement equipment for benchmarking performance of superconducting quantum chips’ was well received. Because quantum chip testing is a relatively new topic for the semiconductor industry, the presentation attracted a sizeable audience of experts on metrology and advanced lithography.

The presentation described the importance of a correlation between end-of-line performance testing and in-line metrology. These aspects become essential with higher number of qubits and more stringent requirements on test time and expected yield. Thorsten shared our observation of the large gap between testing throughput that can be reached by quantum industry players at the moment, compared to the throughput which semicon industry players are used to. It currently takes weeks to test a quantum chip with only about a hundred qubits, while it takes just hours to test devices with millions of transistors.

The questions after the talk centered around how semicon practices can be leveraged for development of quantum chips – especially in testing, because it is such a clear bottleneck in getting quantum chips ready for quantum utility, with a sufficient number and quality of qubits.

Read the abstract of the presentation here: